As is well known in the art, most integrated circuits are manufactured on wafers, typically semiconductor wafers, and more typically silicon wafers. Over the past decades, wafers have grown from a mere two inches in diameter to eight inches in diameter and, more recently, twelve inches in diameter, also known as 300 mm wafers. While most devices manufactured today are manufactured on eight inch wafers, most new integrated device manufacturing facilities will be designed to manufacture on twelve inch wafers.
As the area of a circle is related to the square of its diameter, a fifty percent increase in the diameter (as in moving from an eight inch wafer to a twelve inch wafer) results in more than doubling of the available surface area for manufacturing devices.
Another trend in integrated circuit device manufacturing relates to packaging technology. With the move toward surface mount technology and so called low profile packages, wafers are being ground to increasingly lesser thicknesses as part of the packaging process.
As wafers become larger in diameter and thinner in thickness, previously unknown or at least unappreciated forces play an increasingly important role. These forces include the compressive or tensile stress applied to the wafer by the thin films that are formed thereon as part of the integrated circuit manufacturing processes. Such thin films include dielectric layers, such as so-called inter-layer dielectric (“ILD”), inter-metal dielectric (“IMD”), etch stop layers, passivation layers, and the like, and include conductive layers such as doped polysilicon layers and metal interconnect layers. With modern integrated circuit devices having seven, eight, and even more metal interconnect layers, with the commensurate IMD layers, etch stop layers, and passivation layers at the upper level, twenty or more thin films are typically formed on new generation integrated circuit wafers.
The combination of a greater number of thin films applying stress to thinner wafers results in significant warpage of the wafer and of the subsequently formed integrated circuits (as is known, the wafers are diced into individual chips that, when packaged, form a complete integrated circuit device). FIG. 1a illustrates warping of a semiconductor wafer 2 resulting from the stress applied on the wafer by overlying thin films 4. For purposes of illustration, the multiple conductive, dielectric, and semiconductive films formed over wafer 2 are schematically illustrated as a single layer 4. As described above, these films cumulatively impose a stress on underlying wafer 2 which can cause wafer 2 to warp. The nominal, i.e., non-warped, profile for wafer 2 is illustrated by dotted line 6. The amount of warpage is shown exaggerated for purposes of illustration.
Once wafer 2 is diced into individual chips, or die, the individual die are also warped by the stress imposed by films 4. FIG. 1b illustrates in exaggerated detail the deviation from nominal (dotted line 12) for an exemplary integrated circuit chip 8 warped by stress imposed by films 4.
The warpage caused by films 4 has several deleterious effects. One such effect is an increased difficulty in handling and increased likelihood of breakage for wafer 2 during assembly processes. Another negative effect is that the warpage of chip 8 can significantly impact the electrical performance of the devices formed on chip 8. As is known, strain in the semiconductor layer in which MOS transistors are formed can significantly impact charge carrier mobility. The strain caused by warpage of chip 8 can adversely impact charge carrier mobility.
What is needed, therefore, is a method and structure for overcoming the above described shortcomings in the prior art.